(untitled) (International Journal of Engineering Sciences & Management Research, 2016)
In VLSI System design digital adder with optimum power is one of the important area of research. For many data processing purpose CSA perform fast air thematic function. So, it is clear that there is need to reduce the power consumption in CSA. This paper discusses about to reduce the power dissipation in CSA for many applications. For reduction purpose we use one of the most important approaches, which are Kogge –stone configuration. The proposed design with Kogge-stone adder CSA has reduced power dissipation compared with CMOS technology CSA. The simulation performed using SPICE circuit simulation at 0.18μm technology node & 1.8v standard CMOS process. This comparison with to CMOS logic in 10-100MHz transition frequency shows significant power saving.