(untitled) (International Journal of Engineering Sciences & Management Research, 2016)
A scheme based on error correction coding has been recently proposed to protect parallel FIR filters. In this scheme, each filter is treated as a bit, and redundant filters that act as parity check bits are introduced to detect and correct errors. This reduces the protection overhead and makes the Number of redundant filters independent of the number of parallel filters. The proposed scheme is first described and then illustrated with two case studies. Finally, both the effectiveness in protecting against errors and the cost are evaluated for a field-programmable gate array implementation. This Proposed System Implemented using Verilog HDL and Simulated by Modelsim 6.4 c and Synthesized by Xilinx tool. The proposed system implemented in FPGA Spartan 3 XC3S 200 TQ-144.