A SURVEY ON DESIGN AN EFFICIENT ARCHITECTURE FOR HIGH SPEED CONVOLUTION AND DECONVOLUTION PROCESS

Abstract

In Digital Signal Processing, the convolution and deconvolution with a very long sequence is ubiquitous in many application
areas. They consume much of time. This paper presents a direct method of computing the discrete linear convolution, circular
convolution and deconvolution. The most significant aspect, is the development of a multiplier and divider architecture based
on high speed algorithm. It shows that the implementation of linear convolution and circular convolution is efficient in terms of
area and speed compared to their implementation using conventional multiplier & divider architectures. In this paper we study
different forms of high speed convolution and deconvolution system using FPGA.