ANALYSIS AND REDUCED THE COMPLEXITY OF ADPLL DESIGN ARCHITECTURE WITH K-BEST MIMO DETECTOR UP TO 1.5 GHZ

Abstract

A 7 ps/LSB, 0.02 mm2 and 3.9 mW@50MHz Time to Digital Converter architecture with novel MIMO detector. Which aims to solve the 4 ×4 64-QAM in high-speed applications. Multiple ring oscillators with unique and variable frequencies are used in order to make N independent measurements of the time pulse to be measured M times in order to create transmitter and receiver diversity similar to those in MxN MIMO antenna arrays. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 nm CMOS technology and has 366K gates.